Latency down a wired communication link on an integrated circuit is dependent upon the resistance, capacitance, and current carrying capabilities of the wires within the communication link. Each new process generation of integrated circuit technology scales the technology down by reducing the cross sections of the wires while simultaneously placing them closer together. This increases the number of communication links in a fixed millimeter squared area of an integrated circuit. However, the reduction of the cross sections of the wires in close proximity to each other also modifies the signal carrying properties of the wire.
In a scaled wire, capacitance remains substantially the same but resistance substantially increases due to the reduced cross sectional area. The increased resistance produces a relative increase in the communication latency down a fixed length of wire, such as a 500 micro-meter interconnect. To put this in perspective, assume that every two years a new process generation is created with a scaling factor of 0.7, and that the aspect ratios of wires remain constant. Thus the cross sectional area of wires for each new generation is (0.7)2=0.5, or half that of the previous generation, resulting in a doubling of the wire resistance.
Since wire delay can be approximated as the product of resistance and capacitance (RC), the delay down the same length of wire can double each process generation. In 10 years, 5 process generations have occurred and wire delay down the same distance of interconnect on a scaled wire increases 32 fold (25). Using this assumption, in the last 40 years that the current silicon process technology has been scaled, wire latency would be over a million times greater now than wire latency was in 1972 (assuming no other changes occurred). Various methods have been employed to mitigate reduced wire performance such as better dielectrics, less resistive wire materials, and different aspect ratios. Yet even given the reduced impact from technological innovation to reduce scaling impact on wires, designs built using modern process technologies can have significant limitations due to wire latency.
Reference will now be made to the exemplary embodiments illustrated, and specific language will be used herein to describe the same. It will nevertheless be understood that no limitation of the scope of the invention is thereby intended.